The increasing miniaturization of semiconductor devices has greatly reduced the size of contact holes, which are also referred to as via holes. The advent of 0.18 μm semiconductor processing has produced a myriad of problems such as shape defects caused by insufficient margin in the photolithography step. The etching process becomes increasingly difficult due to the reduced thickness of the photoresist that serves as mask material for etching. Changes in contact dimensions result from the variance of the thickness of interlayer insulation films.
The dielectric layer between the active devices in silicon and the first metal layer is termed the premetal dielectric (PMD). The PMD is also termed the first interlayer dielectric (ILD-1). The PMD is typically a doped silicon dioxide, or glass. An important function of the PMD layer is to isolate transistor devices in two ways: electrically from the metal interconnect layer, and physically from contamination sources such as mobile ions. The PMD has a restricted thermal budget in high-performance devices so as to minimize degrading the transistor's characteristics.
The ILD is an insulating material that electrically separates the metal levels in multilevel metallization. Once deposited, the ILD is patterned an etched to form via pathways for the various metal layers and the silicon. The via holes, also called contact holes, are filled with a metal, conventionally tungsten (W), to form the via hole plug. There are many via holes on a wafer, up to 1011 vias on each individual layer of a 300 mm product wafer. This process of creating via holes in the ILD is repeated for every ILD layer, including the PMD. In conventional metallization, a blanket layer of aluminum alloy metal is deposited on the dielectric layer, patterned and then etched to form metal lines. The metal etch is an important technology in conventional metallization.
FIG. 7 shows a semiconductor device having a via hole manufactured according to the conventional art. In FIG. 7, a transistor has a silicon substrate 1 and a field area 2 that divides one transistor from another. Over the substrate a transistor gate 3 is formed. Over the transistor gate a silicon nitride (Si3N4) passivation layer 4 is formed. Alternatively, silicon oxynitride can be used to form a passivation layer. Over the silicon nitride passivation layer is deposited the BPSC (borophsophosilicate glass) or PMD (premetal dielectric). The materials that can be used for the PMD include FSG (silicon oxyfluoride), HSQ (hydrogen silsesquioxane), nanoporous silica, PAE (polyarylene ether), FLAC (fluorinated amorphous carbon) or AF4 (aliphatic tetrafluorinated poly-p-xylylene).
In the conventional art of FIG. 7, an antireflective coating (ARC) 7 is provided directly on top of the PMD layer 5. Over the ARC 7 is formed a layer of photoresist 8 having openings over the portions where the via holes are to be formed. In the conventional art, a problem arises from the different lengths of the via holes, the via hole over the gate being shorter than the via hole over the source or drain. It is desirable that the via holes be cut straight. However, in the conventional art the photoresist has a wide opening over the via hole and the resulting via hole is tapered. As a result, the diameter l1 of the via hole over the gate and the diameter of the via hole l2 that is not over the gate is not equal so that l1≠l2.
Additional disadvantages associated with the conventional art is that the ARC layer is not completely opaque, and at least some light can penetrate through the ARC. When the phase of the incoming light wave and the phase of the reflective light wave are the same, the intensity of the light equals the sum of the intensities of both the incoming and reflective light. If the phase differs by 180 degrees, then the light cancels each other to cause extinction. The phase can be adjusted by adjusting the thickness of the layer, so that the incoming and reflected light cancel each other.
The difficulty associated with adjusting the ARC layer arises from the subsequent requirement to etch the nitride layer. However, both the ARC and the nitride layer have similar etch characteristics, which means that they both etch at the same speed. As a result, the nitride layer does not act as a mask and the thickness of the ARC layer is difficult to control using the conventional technology.
Additional disadvantages of the conventional technology are associated with the treatment subsequent to opening the via holes. After opening the via hole, Ti and TiN are sputtered to reduce resistance at the contact. Afterwards, the contact hole is filled with tungsten. During the sputtering, Ti and TiN overhang the via hole. This occurs because the sputtering process causes the Ti and TiN to approach the via hole at an angle. As a result, Ti and TiN overhang the via hole to narrow the opening of the via hole. This overhang prevents the tungsten from properly filling the via hole. To prevent this improper filling, the opening can be tapered, but this taper would then result in the associated problem of the diameter of the via hole over the gate being different than the diameter of the via hole not over the gate. Therefore, tapering the via hole does not provide an ideal solution to reduce the disadvantages caused by the Ti and TiN overhang.